Analysis Menu

Layout analysis

With the increase in process density and the number of multilayer metal interconnects, information extraction from the the lower layers requires highly specialized delayering techniques.  LTEC Corporation has developed unique proprietary delayering techniques and highly specialized know-how (trade secrets) that enables our engineers to delayer large areas of deep submicron semiconductor devices uniformly, even beyond 14nm.

 

Example

Design rules analysis of a 0.3mm2 die area, using 14nm technology, are shown.

Metallization:           Cu, Al

Interlayer dielectric:   Organic and inorganic film, low-K.